Prof. Dr. Thorsten Jungmann (last updated 2026-10-13)

Relates to DET-02 Logic operations

Task

With the rules of Boolean algebra, you can transform logic expressions without drawing a circuit. Give all results in the notation of electrical engineering that the lesson uses. Subtasks b) and d) are based on exercises in the textbook by LaMeres [5, p. 146].

a) Write the following expressions in the notation of electrical engineering: from mathematics, !(A && B) || C from computer science and from mathematics.

b) Name the theorem of Boolean algebra that each of the following statements describes, and write it as an equation:

  • (1) A variable combined with itself by OR yields the variable itself.
  • (2) A variable that is negated twice yields the variable itself.
  • (3) A variable combined with 1 by OR yields 1.
  • (4) A variable that appears in several product terms can be factored out.
  • (5) A term that another term of the expression already covers can be removed.
  • (6) An AND gate with inverted inputs is equivalent to an OR gate with an inverted output.

c) Insert all parentheses into that show the order in which the expression is evaluated. Then evaluate for , and .

d) Prove with a proof by exhaustion that an AND gate with inverted inputs is equivalent to an OR gate with an inverted output: .

e) Prove with a truth table that . With OR, the distributive property has no counterpart in ordinary arithmetic.

f) Simplify step by step, and name the theorem that you use in each step.

g) Simplify step by step, and name the theorem that you use in each step.

h) Simplify step by step, and name the theorem that you use in each step.

◀️ Back to the task


Solution

Given

Given explicitly:

  • a) , !(A && B) || C and
  • b) six statements about theorems of Boolean algebra
  • c) ; , and
  • d)
  • e)
  • f) to h) , and

Known:

  • Notations of mathematics, computer science and electrical engineering (DET-02)
  • Precedence: NOT before AND, AND before OR (DET-02)
  • Proof by exhaustion and the theorems with one variable: identity, null element, idempotence, complements and involution (DET-02)
  • Theorems with several variables: commutative, associative and distributive properties, absorption and uniting (DET-02); De Morgan’s laws (DET-02)
  • Transforming an expression step by step (DET-02)
  • The theorems hold for any expressions in place of the variables, for example in place of .

Required

a) the three expressions in the notation of electrical engineering
b) the name and the equation of each theorem
c) the parentheses and the value of
d) and e) the two proofs
f) to h) the simplified expressions, with the theorem of each step

a) Notations

Mathematics writes ∧ for AND, ∨ for OR and ¬ for NOT; computer science writes &&, || and !. In electrical engineering, AND is the dot, OR the plus sign and NOT the bar (DET-02, 5.1). A negation in front of a parenthesis becomes a bar over the whole expression in the parenthesis:

  • !(A && B) || C: !(…) negates the whole parenthesis, && is AND and || is OR, so that the expression becomes

Check by evaluating the original and the new notation for the same values. For , and :

  • and ✓
  • !(A && B) || C becomes !(0 && 1) || 0, that is !0 || 0 and 1 || 0, and thus 1; ✓
  • and ✓

b) Theorems

StatementTheoremEquation
(1)idempotence
(2)involution
(3)null element
(4)distributive property
(5)absorption
(6)De Morgan’s laws

Statement (4) reads the distributive property from right to left (DET-02, 5.4): factoring out is multiplying out in reverse. Statement (6) is the second of De Morgan’s laws, read from right to left (DET-02, 5.5).

Check of (5) with contact logic: a contact lies in parallel with the series of the contacts and . Whenever the series conducts, alone conducts as well, so that the series adds nothing ✓

c) Precedence

Without parentheses, NOT comes first, then AND, then OR (DET-02, 5.2). The bars over and are evaluated first, then the product of and , and finally the sum:

For , and :

Check: with , the term is already 1, and by the null element, whatever and are ✓

Why the precedence matters

Evaluated from left to right, the expression would become . For the same values, , and , it gives – a different result. VHDL knows no precedence between AND and OR; wherever AND and OR are mixed, the parentheses have to be written (DET-02, 5.2).

d) De Morgan’s law

In a proof by exhaustion, both sides are evaluated for every combination of the inputs (DET-02, 5.3):

0011🟢10🟢1
0110🟢01🟢0
1001🟢01🟢0
1100🟢01🟢0

The columns and agree in all four rows: an AND gate with inverted inputs does the same as a NOR gate. This is the second of De Morgan’s laws, .

Check with contact logic: the NOR gate consists of two normally closed contacts in series (DET-02, 4.2). Inverted inputs are normally closed contacts, and AND is a series – the same circuit ✓

e) Distributive property with OR

0000🟢000🟢0
0010🟢001🟢0
0100🟢010🟢0
0111🟢111🟢1
1000🟢111🟢1
1010🟢111🟢1
1100🟢111🟢1
1111🟢111🟢1

The columns and agree in all eight rows; the distributive property with OR holds (DET-02, 5.4).

Check by multiplying out the right-hand side:

✓

f) Simplification of

Each step applies one theorem (DET-02, 5.6):

Check with a truth table:

00🟢0🟢0
01🟢0🟢0
10🟢0🟢0
11🟢1🟢1

The last two columns agree in all rows ✓

g) Simplification of

The term is 1 only where is 1 already; it adds nothing. Then appears once plain and once negated, and has no influence.

Check with a truth table:

🟢000🟢0
🟢001🟢0
🟢010🟢0
🟢011🟢0
🟢100🟢1
🟢101🟢1
🟢110🟢1
🟢111🟢1

The column of agrees with the column in all rows ✓

h) Simplification of

Alternatively, uniting gives the last three steps at once: .

Check with a truth table:

00🟢1🟢1
01🟢0🟢0
10🟢1🟢1
11🟢0🟢0

The last two columns agree in all rows ✓