Exercise DET-02.01 – Forms of representation of the seven gates

Prof. Dr. Thorsten Jungmann (last updated 2026-10-13)

Relates to DET-02 Logic operations

Task

Logic gates make decisions everywhere: in your smartphone, in machines and in the controller of a heat pump. Engineers describe a gate in whichever of seven forms of representation suits the task at hand. In this exercise, you describe each of the seven gates of the lesson in two of these forms, so that you practise each form twice.

All gates except the NOT gate have the two inputs $A$ and $B$; the NOT gate has only the input $A$. The output is always $Y$. Draw schematic symbols according to the standard of the International Electrotechnical Commission (IEC), IEC 60617, and contact logic between the rails L+ and L−. In timing diagrams, the inputs run through all their combinations one after another, in the order of the truth table and each for the same time; assume ideal gates without delay. Give VHDL code as the signal assignment of the output.

a) Draw the contact logic of the NOT gate and sketch its timing diagram.

b) Draw the Karnaugh map of the AND gate and give its VHDL code.

c) Set up the truth table of the OR gate and sketch its timing diagram.

d) Give the logic expression of the NAND gate and draw its contact logic.

e) Draw the schematic symbol of the NOR gate and give its VHDL code.

f) Give the logic expression of the XOR gate and draw its Karnaugh map.

g) Set up the truth table of the XNOR gate and draw its schematic symbol.

Solution

a) contact logic: a normally closed contact $A$ in series with the lamp $Y$; timing diagram: $Y$ is the opposite of $A$, $Y=\overline{A}$
b) Karnaugh map: a single 1, in the cell for $A=1$ and $B=1$; VHDL: Y <= A and B;
c) truth table: $Y$ is 0 only in row 0, where $A$ and $B$ are both 0; timing diagram: $Y$ is 0 only in the first of the four sections
d) $Y=\overline{A\cdot B}$; contact logic: two normally closed contacts $A$ and $B$ in parallel, in series with the lamp $Y$
e) schematic symbol: a rectangle with the qualifying symbol ≥1 and a negation circle at the output; VHDL: Y <= A nor B;
f) $Y=A\oplus B=\overline{A}\cdot B+A\cdot \overline{B}$; Karnaugh map: 1s in the two cells in which $A$ and $B$ differ, diagonally opposite each other
g) truth table: $Y$ is 1 in rows 0 and 3, where $A$ and $B$ are equal; schematic symbol: a rectangle with the qualifying symbol =1 and a negation circle at the output (also = for the equivalence)

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