Exercise DET-02.07 – From VHDL code to the circuit

Prof. Dr. Thorsten Jungmann (last updated 2026-10-13)

Relates to DET-02 Logic operations

Task

Parts of the logic of a heat pump could be described in VHDL, for example for a programmable logic device. You do not need to write such code, but you should recognize it and sketch the circuit that it describes. Subtask a) is based on exercises in the textbook by LaMeres [5, p. 186], subtask e) on a concept check [5, p. 180].

Design 1 releases the compressor:

-- Release of the compressor of a heat pump
entity compressor_release is
  port (D, B : in  bit;   -- D: demand for heat, B: blocking signal of the energy supplier
        R    : out bit);  -- R: compressor released
end entity;
 
architecture behaviour of compressor_release is
begin
  R <= D and not B;
end architecture;

a) Which part of design 1 describes the inputs and outputs, and which part describes the behaviour? Name each port with its direction and its type, and state the values that a port of type bit can take.

b) Sketch the circuit of design 1 according to the standard of the International Electrotechnical Commission (IEC), IEC 60617, and give its logic expression and its truth table.

Design 2 switches on a fault lamp:

-- Fault lamp of a heat pump
entity fault_lamp is
  port (C, P, Q : in  bit;   -- C: collective fault, P: command to switch the pump on,
                             -- Q: feedback that the pump is running
        L       : out bit);  -- L: fault lamp on
end entity;
 
architecture behaviour of fault_lamp is
  signal X1 : bit;           -- intermediate node
begin
  L  <= C or X1;
  X1 <= P xor Q;
end architecture;

c) Sketch the circuit of design 2 according to IEC 60617, and give its logic expression and its truth table, with a column for the intermediate node $X_1$. What does a 1 at $X_1$ tell you about the pump?

d) Which of the following lines does VHDL accept? For each line that it does not accept, give the reason.

• Line 1: Y <= A and B or C;
• Line 2: Y <= (A and B) or C;
• Line 3: Y <= A or B or C;
• Line 4: Y <= A nor B nor C;
• Line 5: Y <= not A and B;

e) In design 2, the output L is assigned before the intermediate node X1 that it uses. Does the circuit change if you swap the two assignments? Give the reason.

Solution

a) The entity compressor_release describes the inputs and outputs, the architecture behaviour the behaviour; D and B are inputs (in) and R is an output (out), all of type bit, which takes only the values 0 and 1
b) An inverter for $B$ and an AND gate: $R=D\cdot \overline{B}$; $R=1$ only for $D=1$ and $B=0$
c) An XOR gate for $P$ and $Q$ with the output $X_1$, then an OR gate for $C$ and $X_1$: $L=C+(P\oplus Q)$; $L$ is 0 only in rows 0 and 3, counting from row 0; a 1 at $X_1$ means that the pump does not follow its command
d) VHDL accepts lines 2, 3 and 5; line 1 mixes and and or without parentheses, and line 4 chains nor, which is not associative
e) No: the assignments are concurrent; each of them describes a gate, and all gates work at the same time, whatever the order of the lines

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