Exercise DET-05.05 – Analysis of given multiplexer and demultiplexer circuits (Solution)

Prof. Dr. Thorsten Jungmann (last updated 2026-11-02)

Relates to DET-05 Codes, code converters and standard components

Task

The three circuits below are drawn according to the standard of the International Electrotechnical Commission (IEC), IEC 60617. In each of them, follow the select inputs to find out what the multiplexers and demultiplexers do, and then fill in the gaps in the truth table. In the symbols, the data inputs and outputs carry their numbers; the data input with the number $k$ is called $I_k$ below.

Circuit 1 has the inputs $A$, $B$ and $C$ and the output $F$.

a) Fill in the gaps.

Row	$A$	$B$	$C$	Selected data input	$F$
0	0	0	0	$I_0$	0
1	0	0	1
2	0	1	0		1
3	0	1	1	$I_1$
4	1	0	0
5	1	0	1	$I_2$
6	1	1	0		0
7	1	1	1

Check your truth table of a) in the simulation of circuit 1.

Open in the simulator

Circuit as text (File → Import From Text…)

<cir f="1" ts="0.000005" ic="1.500424758475255" cb="50" pb="50" vr="5" mts="5e-11">
  <L x="416 368 416 416" f="2"/>
  <L x="384 464 384 512" f="2"/>
  <L x="96 160 48 160" f="2"/>
  <mux x="320 160 448 160" f="0" se="2"/>
  <I x="176 192 240 192" f="0" sl="0.5" hi="5"/>
  <L x="320 224 272 224" f="2" p="1"/>
  <L x="320 256 272 256" f="2"/>
  <M x="448 160 496 160" f="2"/>
  <w x="416 320 416 368" f="0"/>
  <w x="384 320 384 464" f="0"/>
  <w x="96 160 144 160" f="0"/>
  <w x="144 160 320 160" f="0"/>
  <w x="144 160 144 192" f="0"/>
  <w x="144 192 176 192" f="0"/>
  <w x="240 192 320 192" f="0"/>
  <x x="436 422 446 425" f="0" si="16" te="A"/>
  <x x="404 518 414 521" f="0" si="16" te="B"/>
  <x x="16 166 27 169" f="0" si="16" te="C"/>
  <x x="516 166 525 169" f="0" si="16" te="F"/>
  <x x="324 136 447 139" f="0" si="16" te="4-to-1 multiplexer"/>
</cir>

b) Give the minterm list of $F$, and a disjunctive normal form (DNF) that follows directly from the data inputs.

Circuit 2 has the inputs $A$, $B$ and $C$ and the outputs $Y_0$ to $Y_3$ and $Z$.

c) Fill in the gaps.

Row	$A$	$B$	$C$	$Y_0$	$Y_1$	$Y_2$	$Y_3$	$Z$
0	0	0	0	0	0	0	0	0
1	0	0	1			0	0
2	0	1	0			0	0	0
3	0	1	1	0		0	0
4	1	0	0	0	0	0	0
5	1	0	1	0	0		0
6	1	1	0	0	0	0		0
7	1	1	1	0	0	0

Check your truth table of c) in the simulation of circuit 2.

Open in the simulator

Circuit as text (File → Import From Text…)

<cir f="1" ts="0.000005" ic="1.500424758475255" cb="50" pb="50" vr="5" mts="5e-11">
  <L x="384 368 384 416" f="2"/>
  <L x="352 464 352 512" f="2"/>
  <dmux x="320 160 448 160" f="0" se="2"/>
  <L x="320 160 272 160" f="2"/>
  <M x="592 160 640 160" f="2"/>
  <M x="592 192 640 192" f="2"/>
  <M x="592 224 640 224" f="2"/>
  <M x="592 256 640 256" f="2"/>
  <Or x="592 416 736 416" f="0"/>
  <M x="784 416 832 416" f="2"/>
  <w x="384 320 384 368" f="0"/>
  <w x="352 320 352 464" f="0"/>
  <w x="448 160 592 160" f="0"/>
  <w x="448 192 512 192" f="0"/>
  <w x="512 192 592 192" f="0"/>
  <w x="512 192 512 400" f="0"/>
  <w x="512 400 592 400" f="0"/>
  <w x="448 224 480 224" f="0"/>
  <w x="480 224 592 224" f="0"/>
  <w x="480 224 480 432" f="0"/>
  <w x="480 432 592 432" f="0"/>
  <w x="448 256 592 256" f="0"/>
  <w x="736 416 784 416" f="0"/>
  <x x="404 422 414 425" f="0" si="16" te="A"/>
  <x x="372 518 382 521" f="0" si="16" te="B"/>
  <x x="240 166 251 169" f="0" si="16" te="C"/>
  <x x="660 166 679 169" f="0" si="16" te="Y0"/>
  <x x="660 198 679 201" f="0" si="16" te="Y1"/>
  <x x="660 230 679 233" f="0" si="16" te="Y2"/>
  <x x="660 262 679 265" f="0" si="16" te="Y3"/>
  <x x="852 422 861 425" f="0" si="16" te="Z"/>
  <x x="324 136 465 139" f="0" si="16" te="1-to-4 demultiplexer"/>
</cir>

d) Give the logic expression of $Z$. For which inputs is $Z=1$? Say it in one sentence.

Circuit 3 sends four fixed data inputs over one line $L$. It has the inputs $S_1$, $S_0$, $T_1$ and $T_0$ and the outputs $L$ and $Q_0$ to $Q_3$.

e) Fill in the gaps.

$S_1$	$S_0$	$T_1$	$T_0$	$L$	$Q_0$	$Q_1$	$Q_2$	$Q_3$
0	0	0	0	1	1	0	0	0
0	1	0	1				0	0
1	0	1	0	1	0	0		0
1	1	1	1		0	0	0
0	0	1	0			0		0
0	1	0	0			0	0	0
1	1	0	1	1	0		0	0
1	0	1	1		0	0	0

Check your truth table of e) in the simulation of circuit 3.

Open in the simulator

Circuit as text (File → Import From Text…)

<cir f="1" ts="0.000005" ic="1.500424758475255" cb="50" pb="50" vr="5" mts="5e-11">
  <L x="352 368 352 416" f="2"/>
  <L x="320 464 320 512" f="2"/>
  <L x="640 368 640 416" f="2"/>
  <L x="608 464 608 512" f="2"/>
  <mux x="256 160 384 160" f="0" se="2"/>
  <dmux x="576 160 704 160" f="0" se="2"/>
  <L x="256 160 208 160" f="2" p="1"/>
  <L x="256 192 208 192" f="2"/>
  <L x="256 224 208 224" f="2" p="1"/>
  <L x="256 256 208 256" f="2" p="1"/>
  <M x="480 144 480 96" f="2"/>
  <M x="752 160 800 160" f="2"/>
  <M x="752 192 800 192" f="2"/>
  <M x="752 224 800 224" f="2"/>
  <M x="752 256 800 256" f="2"/>
  <w x="352 320 352 368" f="0"/>
  <w x="320 320 320 464" f="0"/>
  <w x="640 320 640 368" f="0"/>
  <w x="608 320 608 464" f="0"/>
  <w x="384 160 480 160" f="0"/>
  <w x="480 160 576 160" f="0"/>
  <w x="480 144 480 160" f="0"/>
  <w x="704 160 752 160" f="0"/>
  <w x="704 192 752 192" f="0"/>
  <w x="704 224 752 224" f="0"/>
  <w x="704 256 752 256" f="0"/>
  <x x="372 422 391 425" f="0" si="16" te="S1"/>
  <x x="340 518 359 521" f="0" si="16" te="S0"/>
  <x x="660 422 678 425" f="0" si="16" te="T1"/>
  <x x="628 518 646 521" f="0" si="16" te="T0"/>
  <x x="500 102 508 105" f="0" si="16" te="L"/>
  <x x="820 166 841 169" f="0" si="16" te="Q0"/>
  <x x="820 198 841 201" f="0" si="16" te="Q1"/>
  <x x="820 230 841 233" f="0" si="16" te="Q2"/>
  <x x="820 262 841 265" f="0" si="16" te="Q3"/>
</cir>

f) Under which condition does each output $Q_k$ show exactly its own data input $I_k$, and what happens otherwise? How would you have to drive the select inputs for all four signals to share the line $L$?

◀️ Back to the task

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Solution

Given

Given explicitly:

• the three circuits with their inputs and outputs; in circuit 3 the data inputs 1, 0, 1 and 1
• the truth tables with gaps

Known:

• Multiplexer with $n$ select inputs: it passes the data input whose number the select inputs form (DET-05)
• Demultiplexer: it routes its input to the output whose number the select inputs form; the other outputs are 0; with its input at 1, it works as a decoder (DET-05)
• Multiplexer as a function generator with 0, 1, $C$ or $\overline{C}$ at the data inputs (DET-05)
• Multiplexer and demultiplexer over a single line (DET-05)

Required

a), c) and e) the complete truth tables
b) the minterm list and a disjunctive normal form (DNF) of $F$
d) the expression of $Z$ and when $Z=1$
f) the condition for correct transmission, and how all signals share the line

a) Circuit 1: truth table

$A$ has the weight 2 and $B$ the weight 1 (DET-05, 5.1), so they select $I_{2A+B}$. In the rows with $A=0$ and $B=0$, the multiplexer passes $I_0=C$; with $A=0$ and $B=1$, $I_1=\overline{C}$; with $A=1$ and $B=0$, $I_2=1$; with $A=1$ and $B=1$, $I_3=0$. So in row 1, with $A=0$, $B=0$ and $C=1$, it passes $I_0$, and the output is 1.

Row	$A$	$B$	$C$	Selected data input	$F$
0	0	0	0	$I_0$	0
1	0	0	1	$I_0$	1
2	0	1	0	$I_1$	1
3	0	1	1	$I_1$	0
4	1	0	0	$I_2$	1
5	1	0	1	$I_2$	1
6	1	1	0	$I_3$	0
7	1	1	1	$I_3$	0

b) Circuit 1: minterm list and DNF

The output is 1 in the rows 1, 2, 4 and 5:

$$F(A,B,C)=\sum m(1,2,4,5)$$

A DNF follows directly from the data inputs: each select combination contributes its data input (DET-05, 5.1, DET-05, 6.2). $I_0=C$ gives the term $\overline{A}\cdot \overline{B}\cdot C$, $I_1=\overline{C}$ gives $\overline{A}\cdot B\cdot \overline{C}$, $I_2=1$ gives $A\cdot \overline{B}$, and $I_3=0$ gives nothing:

$$F=\overline{A}\cdot \overline{B}\cdot C+\overline{A}\cdot B\cdot \overline{C}+A\cdot \overline{B}$$

Check with row 5, with $A=1$, $B=0$ and $C=1$: the multiplexer passes $I_2=1$, and the expression gives $F=0+0+1\cdot 1=1$ ✓

c) Circuit 2: truth table

The demultiplexer routes $C$ to the output $Y_{2A+B}$, and the other outputs are 0 (DET-05, 5.2):

$$\begin{array}{rl}{Y}_0& =\overline{A}\cdot \overline{B}\cdot C\\ Y_1& =\overline{A}\cdot B\cdot C\\ Y_2& =A\cdot \overline{B}\cdot C\\ Y_3& =A\cdot B\cdot C\\ Z& =Y_1+Y_2\end{array}$$

Row	$A$	$B$	$C$	$Y_0$	$Y_1$	$Y_2$	$Y_3$	$Z$
0	0	0	0	0	0	0	0	0
1	0	0	1	1	0	0	0	0
2	0	1	0	0	0	0	0	0
3	0	1	1	0	1	0	0	1
4	1	0	0	0	0	0	0	0
5	1	0	1	0	0	1	0	1
6	1	1	0	0	0	0	0	0
7	1	1	1	0	0	0	1	0

For $C=0$, all outputs are 0, whichever output the select inputs choose.

d) Circuit 2: expression of $Z$

$$\begin{array}{rl}{Y}_1& =\overline{A}\cdot B\cdot C\\ Y_2& =A\cdot \overline{B}\cdot C\\ Z& =Y_1+Y_2=\overline{A}\cdot B\cdot C+A\cdot \overline{B}\cdot C=(A\oplus B)\cdot C\end{array}$$

$Z$ is 1 if $C$ is 1 and $A$ and $B$ differ: rows 3 and 5 of the table ✓

e) Circuit 3: truth table

The multiplexer passes the data input that $S_1$ and $S_0$ select, so the line carries $L=I_{2S_1+S_0}$. With the data inputs 1, 0, 1 and 1, this is 0 only for $S_1=0$ and $S_0=1$:

$$\begin{array}{rl}L& =\overline{S_0}+S_1\\ Q_0& =\overline{T_1}\cdot \overline{T_0}\cdot L\\ Q_1& =\overline{T_1}\cdot T_0\cdot L\\ Q_2& =T_1\cdot \overline{T_0}\cdot L\\ Q_3& =T_1\cdot T_0\cdot L\end{array}$$

$S_1$	$S_0$	$T_1$	$T_0$	$L$	$Q_0$	$Q_1$	$Q_2$	$Q_3$
0	0	0	0	1	1	0	0	0
0	1	0	1	0	0	0	0	0
1	0	1	0	1	0	0	1	0
1	1	1	1	1	0	0	0	1
0	0	1	0	1	0	0	1	0
0	1	0	0	0	0	0	0	0
1	1	0	1	1	0	1	0	0
1	0	1	1	1	0	0	0	1

f) Circuit 3: sharing a line

In the first four rows, $S_1$ and $S_0$ carry the same number as $T_1$ and $T_0$. There, $Q_k$ shows exactly its own data input: $Q_0=1$, $Q_1=0$, $Q_2=1$ and $Q_3=1$. In the other rows, the numbers differ, and the signal of one data input arrives at the output of another: in the row with $S_1=1$, $S_0=1$, $T_1=0$ and $T_0=1$, for example, $I_3=1$ arrives at $Q_1$, whose own data input is $I_1=0$.

For all four signals to share the line, both pairs of select inputs have to run through the numbers 0 to 3 together, again and again. Each data input then gets its own time slot on the single line: time-division multiplexing (DET-05, 5.3).