Exercise DET-04.04 – Hazards (Solution)

Prof. Dr. Thorsten Jungmann (last updated 2026-10-25)

Relates to DET-04 Algorithmic minimization of functions with many inputs and hazard analysis

Task

Different paths through a circuit have different delays. While the inputs change, the output of a circuit whose truth table is correct can therefore show short, unwanted pulses. In each function, the first variable has the highest weight.

a) Describe the situation in which a static 1 hazard can occur, and the situation in which a static 0 hazard can occur.

b) The function $F_{1} (A, B, C) = \sum m (1, 3, 6, 7)$ is built as a two-level circuit from its minimal disjunctive normal form (DNF), $F_{1} = \overline{A} \cdot C + A \cdot B$ , with an inverter for $A$ . Find the change of a single input that can cause a static 1 hazard. Which values do the other inputs have?

c) Each gate, the inverter included, has a propagation delay of 10 ns. At $t = 0$ , $A$ falls from 1 to 0, while the other inputs keep the values found in b). Draw the timing diagram of $A$ , $\overline{A}$ , $\overline{A} \cdot C$ , $A \cdot B$ and $F_{1}$ . How long does the dip last, and after what time has the output reached its final value for good?

d) Make the circuit of b) free of this hazard with an additional product term. Why is the circuit then no longer minimal?

e) The minimal DNF of $F_{2} (A, B, C, D) = \sum m (0, 1, 2, 3, 7, 8, 12, 15)$ is $F_{2} = \overline{A} \cdot \overline{B} + B \cdot C \cdot D + A \cdot \overline{C} \cdot \overline{D}$ . Find all changes of a single input that can cause a static 1 hazard in its two-level circuit, and make the circuit free of them.

f) In the circuit $F_{3} = A + B$ , both inputs change at the same moment: $A$ from 1 to 0 and $B$ from 0 to 1. What can the output do? Can an additional term prevent it?

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Solution

Given

Given explicitly:

b) to d) $F_{1} (A, B, C) = \sum m (1, 3, 6, 7)$ with the minimal DNF $F_{1} = \overline{A} \cdot C + A \cdot B$ , built as a two-level circuit with an inverter for $A$
c) a propagation delay of 10 ns for each gate, the inverter included; $A$ falls from 1 to 0 at $t = 0$
e) $F_{2} (A, B, C, D) = \sum m (0, 1, 2, 3, 7, 8, 12, 15)$ with the minimal DNF $F_{2} = \overline{A} \cdot \overline{B} + B \cdot C \cdot D + A \cdot \overline{C} \cdot \overline{D}$
f) $F_{3} = A + B$ ; $A$ falls from 1 to 0 and $B$ rises from 0 to 1 at the same moment

Known:

Static 1 hazard, static 0 hazard and dynamic hazard (DET-04)
The race between two paths; two neighbouring ones in different loops as the mark of a logic hazard in a two-level circuit (DET-04)
Hazard analysis: a variable that appears as it is in one product term and negated in another; redundant prime implicants that unite the separate prime implicants (DET-04)
Redundant prime implicants: all their ones lie in the essential prime implicants (DET-04)
Function hazard: several inputs change at once (DET-04)
Delays add up along each path; the delay of a circuit is the delay of its longest path (DET-02)
Neighbours in the Karnaugh map, also across the edges (DET-03)

Required

a) the situations in which a static 1 hazard and a static 0 hazard can occur
b) the change of a single input that can cause a static 1 hazard in $F_{1}$ , with the values of the other inputs
c) the timing diagram, the duration of the dip and the time after which the output has reached its final value
d) the hazard-free form of $F_{1}$ and the reason why it is no longer minimal
e) all changes of a single input that can cause a static 1 hazard in $F_{2}$ , and the hazard-free form
f) what the output of $F_{3}$ can do, and whether an additional term can prevent it

a) Static 1 and static 0 hazards

Hazards are named after what the output should do (DET-04, 4.1). A static 1 hazard can occur when the inputs change from one combination for which the output is 1 to another combination for which the output is 1 as well. The output should stay 1, but because different paths have different delays, it drops to 0 for a moment.

A static 0 hazard can occur when the inputs change between two combinations for which the output is 0. The output should stay 0, but it rises to 1 for a moment.

b) Finding the hazard

In a two-level circuit, a logic hazard shows up as two neighbouring ones that do not lie in a common loop of the minimal DNF (DET-04, 4.2). It helps to look for a variable that appears as it is in one product term and negated in another (DET-04, 4.3). In $F_{1} = \overline{A} \cdot C + A \cdot B$ , only $A$ does: negated in $\overline{A} \cdot C$ , as it is in $A \cdot B$ . If the other variables are set so that both terms reduce to this variable, the expression becomes $\overline{A} + A$ . For $B = 1$ and $C = 1$ :

F_{1} = \overline{A} \cdot C + A \cdot B = \overline{A} \cdot 1 + A \cdot 1 = \overline{A} + A

In theory, $\overline{A} + A$ is always 1, but while $A$ changes, the output can be 0 for a moment. In the map (figure), the change of $A$ leads between the cell of minterm 7 (111) and the neighbouring cell of minterm 3 (011). Both cells contain a one, but they lie in different loops, $A \cdot B$ and $\overline{A} \cdot C$ : a static 1 hazard can occur when $A$ changes while $B = 1$ and $C = 1$ .

Karnaugh map of F1 with the loops A bar C and A B of the minimal form and an arrow for the change of A from 1 to 0 from the cell of minterm 7 to the neighbouring cell of minterm 3 in the other loop

c) Timing diagram

The output of the two-level circuit is

F_{1} = \overline{A} \cdot C + A \cdot B

Follow the change through the circuit, gate by gate, as in the lesson (DET-04, 4.2), with $B = 1$ and $C = 1$ (figure):

At $t = 0$ , $A$ falls from 1 to 0.
After 10 ns, the output of the AND gate for $A \cdot B$ has followed and is 0; at the same time, the output of the inverter, $\overline{A}$ , rises to 1.
The AND gate for $\overline{A} \cdot C$ needs another 10 ns, so its output rises only after 20 ns.
Between 10 ns and 20 ns, both inputs of the OR gate are 0. With its own delay, the output $F_{1}$ is 0 from 20 ns to 30 ns.

Timing diagram of the change of A from 1 to 0 with B and C at 1, in which A bar and A B change after 10 ns, A bar C after 20 ns and F1 drops to 0 between 20 ns and 30 ns, a static 1 hazard

The dip lasts

t_{dip} = 30 ns - 20 ns = 10 ns

The output has reached its final value for good when the change has passed the longest path of the circuit, from $A$ through the inverter, the AND gate for $\overline{A} \cdot C$ and the OR gate (DET-02, 6.3). This path has three gates:

t_{final} = 3 \cdot 10 ns = 30 ns

So you have to wait for the delay of the longest path until all hazards have settled. When $A$ rises instead, $A \cdot B$ becomes 1 after 10 ns, before $\overline{A} \cdot C$ becomes 0 after 20 ns, and with these delays, there is no dip.

Check by counting the gates on the two paths of $A$ to the output: the direct path through the AND gate for $A \cdot B$ and the OR gate has two gates, $2 \cdot 10 ns = 20 ns$ , the time at which the dip begins; the path through the inverter has three, $3 \cdot 10 ns = 30 ns$ , the time at which it ends ✓

d) Removing the hazard

A redundant prime implicant that unites the two separate loops removes the hazard (DET-04, 4.3). The cells of minterms 3 and 7 form the loop $B \cdot C$ (figure, dashed): there, $B$ and $C$ are 1, while $A$ changes. It is a prime implicant of $F_{1}$ , but a redundant one, because its ones already lie in $\overline{A} \cdot C$ and $A \cdot B$ (DET-04, 1.2). Added to the minimal DNF, it makes the circuit free of this logic hazard:

F_{1} = \overline{A} \cdot C + A \cdot B + B \cdot C

Karnaugh map of F1 with the loops A bar C and A B of the minimal form and the redundant prime implicant B C as a dashed loop that unites them

While $A$ changes with $B = 1$ and $C = 1$ , the new term does not depend on $A$ and holds the output at 1, however the delays turn out. Check for $B = 1$ and $C = 1$ :

B \cdot C = 1 \cdot 1 = 1

✓

The price is an additional AND gate with two inputs and a third input of the OR gate. The circuit needs more gates than its minimal DNF, so it is no longer minimal; it is the complete sum of all three prime implicants of $F_{1}$ .

e) Four inputs

In $F_{2} = \overline{A} \cdot \overline{B} + B \cdot C \cdot D + A \cdot \overline{C} \cdot \overline{D}$ , all four variables appear both as they are and negated. A change of a single input can only lead from one term to another if the two terms differ in this variable alone (DET-04, 4.3):

$A$ is negated in $\overline{A} \cdot \overline{B}$ and appears as it is in $A \cdot \overline{C} \cdot \overline{D}$ . With $B = 0$ , $C = 0$ and $D = 0$ , both terms reduce to $\overline{A}$ and $A$ . The change of $A$ leads between minterm 0 (0000) and minterm 8 (1000); in the map, these two cells are neighbours across the top and the bottom edge (DET-03, 4.1), and they lie in different loops.
$B$ is negated in $\overline{A} \cdot \overline{B}$ and appears as it is in $B \cdot C \cdot D$ . With $A = 0$ , $C = 1$ and $D = 1$ , both terms reduce to $\overline{B}$ and $B$ . The change of $B$ leads between minterm 3 (0011) and minterm 7 (0111), which lie in different loops.
$C$ and $D$ appear as they are in $B \cdot C \cdot D$ and negated in $A \cdot \overline{C} \cdot \overline{D}$ . These two terms differ in both variables, so no change of a single input leads from one to the other.

For $B = 0$ , $C = 0$ and $D = 0$ :

F_{2} = \overline{A} \cdot \overline{B} + B \cdot C \cdot D + A \cdot \overline{C} \cdot \overline{D} = \overline{A} \cdot \overline{0} + 0 \cdot 0 \cdot 0 + A \cdot \overline{0} \cdot \overline{0} = \overline{A} + A

For $A = 0$ , $C = 1$ and $D = 1$ :

F_{2} = \overline{A} \cdot \overline{B} + B \cdot C \cdot D + A \cdot \overline{C} \cdot \overline{D} = \overline{0} \cdot \overline{B} + B \cdot 1 \cdot 1 + 0 \cdot \overline{1} \cdot \overline{1} = \overline{B} + B

Two redundant prime implicants unite the separate loops (figure, dashed): $\overline{B} \cdot \overline{C} \cdot \overline{D}$ with the cells of minterms 0 and 8, and $\overline{A} \cdot C \cdot D$ with the cells of minterms 3 and 7. Added to the minimal DNF, they make the circuit free of logic hazards:

F_{2} = \overline{A} \cdot \overline{B} + B \cdot C \cdot D + A \cdot \overline{C} \cdot \overline{D} + \overline{B} \cdot \overline{C} \cdot \overline{D} + \overline{A} \cdot C \cdot D

Karnaugh map of F2 with the loops A bar B bar, B C D and A C bar D bar of the minimal form and the two added prime implicants B bar C bar D bar and A bar C D as dashed loops

Check for the change of $A$ , with $B = 0$ , $C = 0$ and $D = 0$ :

\overline{B} \cdot \overline{C} \cdot \overline{D} = \overline{0} \cdot \overline{0} \cdot \overline{0} = 1

Check for the change of $B$ , with $A = 0$ , $C = 1$ and $D = 1$ :

\overline{A} \cdot C \cdot D = \overline{0} \cdot 1 \cdot 1 = 1

Both added terms stay 1, whatever the changing input does ✓

The two added terms are the remaining prime implicants of $F_{2}$ ; the hazard-free form is the complete sum of all five.

f) Two inputs at once

Here, two inputs change at the same moment, and their changes never arrive at exactly the same time. If $A$ falls before $B$ rises, the OR gate sees $A = 0$ and $B = 0$ for a moment:

F_{3} = A + B = 0 + 0 = 0

Before and after the change, $F_{3}$ is 1, so the output drops to 0 for a moment: a static 1 hazard. Because it is caused by the change of several inputs, it is a function hazard (DET-04, 4.4). If $B$ rises first, the gate sees $A = 1$ and $B = 1$ for a moment, and the output stays 1.

No additional term can prevent the dip. On its way, the circuit passes through the combination $A = 0$ , $B = 0$ , for which the function itself demands $F_{3} = 0$ . To hold the output at 1, a term would have to be 1 for exactly this combination, and it would change the function. The dip is avoided by reading the output only when all changes have settled, or by making sure that the inputs never change at the same time (DET-04, 4.4).

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